HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 176

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 6 Interrupt Controller (INTC)
6.4.3
The interrupt control register 1 (ICR1) is a 16-bit register that specifies the detection mode to
external interrupt input pins, IRQ0 to IRQ5 individually: rising edge, falling edge, or low level.
Rev. 5.00 May 29, 2006 page 126 of 698
REJ09B0146-0500
Bit
15
14
13
12
Bit Name
MAI
IRQLVL
BLMSK
—
Interrupt Control Register 1 (ICR1)
Initial Value
0
1
0
0
R/W
R/W
R/W
R/W
R
Description
Mask All Interrupts
When set to 1, masks all interrupt requests when a
low level is being input to the NMI pin. Masks NMI
interrupts in standby mode.
0: All interrupt requests are not masked when a low
1: All interrupt requests are masked when a low
Interrupt Request Level Detect
Selects whether the IRQ3 to IRQ0 pins are used as
four independent interrupt pins or as 15-level
interrupt pins encoded as IRL3 to IRL0.
0: Used as four independent interrupt request pins
1: Used as encoded 15-level interrupt pins as IRL3
BL Bit Mask
Specifies whether NMI interrupts are masked when
the BL bit of the SR register is 1.
0: NMI interrupts are masked when the BL bit is 1
1: NMI interrupts are accepted regardless of the BL
Reserved
This bit is always read as 0. The write value should
always be 0.
level is being input to the NMI pin
level is being input to the NMI pin
IRQ3 to IRQ0
to IRL0
bit setting