HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 47

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 6.7
Section 7 User Break Controller
Table 7.1
Section 8 Bus State Controller (BSC)
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Table 8.6
Table 8.7
Table 8.8
Table 8.9
Table 8.10
Table 8.11
Table 8.12
Table 8.13
Table 8.14
Table 8.15
Table 8.16
Table 8.17
Table 8.18
Section 9 Direct Memory Access Controller (DMAC)
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.6
Table 9.7
Table 9.8
Section 10 Clock Pulse Generator (CPG)
Table 10.1
Table 10.2
Interrupt Response Time ........................................................................................ 136
Data Access Cycle Addresses and Operand Size Comparison Conditions ............ 154
Pin Configuration ................................................................................................... 165
Physical Address Space Map ................................................................................. 168
Correspondence between External Pins (MD4 and MD3) and Memory Size ........ 169
PCMCIA Interface Characteristics......................................................................... 170
PCMCIA Support Interface.................................................................................... 171
Area 6 Wait Control (Normal Memory I/F) ........................................................... 184
Area 5 Wait Control (Normal Memory I/F) ........................................................... 184
Area 4 Wait Control ............................................................................................... 185
Area 0 Wait Control ............................................................................................... 185
Area 6 Wait Control (PCMCIA I/F)....................................................................... 192
32-Bit External Device/Big Endian Access and Data Alignment .......................... 198
16-Bit External Device/Big Endian Access and Data Alignment .......................... 198
8-Bit External Device/Big Endian Access and Data Alignment ............................ 199
32-Bit External Device/Little Endian Access and Data Alignment ....................... 200
16-Bit External Device/Little Endian Access and Data Alignment ....................... 200
8-Bit External Device/Little Endian Access and Data Alignment ......................... 201
Relationship between Bus Width, AMX, and Address Multiplex Output.............. 214
Example of Correspondence between this LSI and Synchronous DRAM
Address Pins (AMX (3 to 0) = 0100 (32-Bit Bus Width)) ..................................... 215
Pin Configuration ................................................................................................... 254
Selecting External Request Modes with the RS Bits.............................................. 267
Selecting On-Chip Peripheral Module Request Modes with the RS Bit ................ 268
Supported DMA Transfers ..................................................................................... 272
Relationship of Request Modes and Bus Modes by DMA Transfer Category....... 283
Transfer Conditions and Register Settings for Transfer between On-Chip A/D
Converter and External Memory ............................................................................ 298
Values in the DMAC after the Fourth Transfer Ends............................................. 299
Transfer Conditions and Register Settings for Transfer between External
Memory and SCIF Transmitter .............................................................................. 300
Clock Pulse Generator Pins and Functions............................................................. 306
Clock Operating Modes.......................................................................................... 307
Rev. 5.00 May 29, 2006 page xlv of xlviii