HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 212

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 7 User Break Controller
7.4
1. Only CPU can read/write UBC registers.
2. UBC cannot monitor CPU and DMAC access in the same channel.
3. Notes in specification of sequential break are described below:
4. The change of a UBC register value is executed in MA (memory access) stage. Therefore,
5. The branch instruction should not be executed as soon as PC trace register BRSR and BRDR
6. When PC breaks and TLB exceptions or errors occur in the same instruction. The priority is as
Rev. 5.00 May 29, 2006 page 162 of 698
REJ09B0146-0500
A. A condition match occurs when a channel B match occurs in a bus cycle after a channel A
B. Since the CPU has a pipeline configuration, the pipeline determines the order of an
C. When the bus cycle condition for channel A is specified as a break before execution
even if the break condition matches in the instruction fetch address following the instruction in
which the pre-execution break is specified as the break condition, no break occurs. In order to
know the timing UBC register is changed, read the last written register. Instructions after then
are valid for the newly written register value.
are read.
follows:
A. Break and instruction fetch exceptions: Instruction fetch exception occurs first.
B. Break before execution and operand exception: Break before execution occurs first.
C. Break after execution and operand exception: Operand exception occurs first.
match occurs in another bus cycle in sequential break setting. Therefore, no condition
match occurs even if a bus cycle, in which a channel A match and a channel B match occur
simultaneously, is set.
instruction fetch cycle and a memory cycle. Therefore, when a channel condition matches
in the order of bus cycles, a sequential condition is satisfied.
(PCBA = 0 in BRCR) and an instruction fetch cycle (in BBRA), the attention is as follows.
A break is issued and condition match flags in BRCR are set to 1, when the bus cycle
conditions both for channels A and B match simultaneously.
Usage Note