HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 146

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Exception Processing
Rev. 5.00 May 29, 2006 page 96 of 698
REJ09B0146-0500
IRL Interrupts
IRQ Pin Interrupts
On-Chip Peripheral Module Interrupts
H-UDI Interrupt
Conditions: The value of the interrupt mask bits in SR is lower than the IRL3 to IRL0 level
and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. SR
at the time the interrupt is accepted is saved to SSR. The code corresponding to the
IRL3 to IRL0 level is set in INTEVT and INTEVT2. The corresponding code is given as
H'200 + B' (IRL3–IRL0)
and RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. The received level is
not set in the interrupt mask bit of SR. See section 6, Interrupt Controller (INTC), for more
information.
Conditions: IRQ pin is asserted and the interrupt mask bit of SR is lower than the IRQ
priority level and the BL bit in SR is 0. The interrupt is accepted at an instruction
boundary.
Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The
SR at the point the interrupt is accepted is saved to the SSR. The code corresponding to the
interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are
set to 1 and a branch occurs to VBR + H'0600. The received level is not set to the interrupt
mask bit of SR. See section 6, Interrupt Controller (INTC), for more information.
Conditions: The interrupt mask bit of SR is lower than the on-chip peripheral module
(TMU, RTC, SCI0, SCI2, A/D, LCDC, PCC, DMAC, WDT, REF) interrupt level and the
BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The
SR at the point the interrupt is accepted is saved to the SSR. The code corresponding to the
interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are
set to 1 and a branch occurs to VBR + H'0600. See section 6, Interrupt Controller (INTC),
for more information.
the interrupt mask bit of SR is lower than 15 and the BL bit in SR is 0. The interrupt is
accepted at an instruction boundary.
SR at the point the interrupt is accepted is saved to the SSR. H'5E0 is set to INTEVT and
INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to VBR +
H'0600. See section 6, Interrupt Controller (INTC), for more information.
Conditions: H-UDI interrupt command is input (see section 21.4.4, H-UDI Interrupt) and
Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The
H'20. See table 6.4 for the corresponding code. The BL, MD,