HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 272

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 8 Bus State Controller (BSC)
A Tnop cycle, in which no operation is performed, is inserted before the Tc1 cycle in which the
READ command is issued in figure 8.19, but when synchronous DRAM is read, there is a two-
cycle latency for the DQMxx signal that performs the byte specification. If the Tc1 cycle were
performed immediately, without inserting a Tnop cycle, it would not be possible to perform the
DQMxx signal specification for Td1 cycle data output. This is the reason for inserting the Tnop
cycle. If the CAS latency is two cycles or longer, Tnop cycle insertion is not performed, since the
timing requirements will be met even if the DQMxx signal is set after the Tc1 cycle.
When bank active mode is set, if only accesses to the respective banks in the area 3 space are
considered, as long as accesses to the same row address continue, the operation starts with the
cycle in figure 8.18 or 8.21, followed by repetition of the cycle in figure 8.19 or 8.22. An access to
a different area 3 space during this time has no effect. If there is an access to a different row
address in the bank active state, after this is detected the bus cycle in figure 8.19 or 8.22 is
executed instead of that in figure 8.19 or 8.22. In bank active mode, too, all banks become inactive
after a refresh cycle or after the bus is released as the result of bus arbitration.
If an external bus access request (in order to perform 2) below conflicts with an auto-refresh
request, self-refresh request, or bus release request internal to the LSI under the following
conditions, SDRAM all-bank precharge may not be executed properly in the first cycle of the
refresh or bus release cycle. In this case, precharging of the selected bank is executed instead of
all-bank precharge.
1. The RASD bit in the individual memory control register (MCR) is set to 1
and
2. long-word access is performed to any 16-bit bus width area (areas 0 to 6) or word/long-word
access is performed to any 8-bit bus width area (areas 0 to 6).
The problem may be avoided by either of the following measures.
1. Use the auto-precharge mode.
2. Use 32-bit bus width for all areas.
Rev. 5.00 May 29, 2006 page 222 of 698
REJ09B0146-0500