HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 469

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is
output from the TxD0 pin.
TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit
of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND
flag has been confirmed, the stop bit will be in the process of transmission and will not be
transmitted normally. Therefore, the TE bit should not be cleared to 0 for at least 0.5 serial clock
cycles (or 1.5 cycles if two stop bits are used) after setting of the TEND flag setting is confirmed.
Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only): When a
receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if
TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that
clearing RE to 0 does not clear the receive error flags.
Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode: In the
asynchronous mode, the SCI operates on a base clock of 16 times the transfer rate frequency. In
receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples
on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure
14.24).
Basic clock
Receive
data (RxD0)
Synchronization
sampling timing
Data sampling
timing
Figure 14.24 Receive Data Sampling Timing in Asynchronous Mode
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
8 clocks
Start bit
16 clocks
–7.5 clocks
Section 14 Serial Communication Interface (SCI)
+7.5 clocks
Rev. 5.00 May 29, 2006 page 419 of 698
D0
REJ09B0146-0500
D1