HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 134

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Exception Processing
All general exception events occur in a relative order in the execution sequence of an instruction
(i.e. execution order), but are handled at priority level 2 in instruction-stream order (i.e. program
order), where an exception detected in a preceding instruction is accepted prior to an exception
detected in a subsequent instruction.
Three general exception events (reserved instruction code exception, unconditional trap, and
illegal slot instruction exception) are detected in the decode stage (ID stage) of different
instructions and are mutually exclusive events in the instruction pipeline. They have the same
execution priority. Figure 4.2 shows the order of general exception acceptance.
Rev. 5.00 May 29, 2006 page 84 of 698
REJ09B0146-0500
Figure 4.2 Example of Acceptance Order of General Exceptions
Pipeline Sequence:
Instruction n
Instruction n + 1
Instruction n + 2
Detection Order:
TLB miss (instruction n+1)
TLB miss (instruction n) and RIE (instruction n + 2) = simultaneous detection
Handling Order:
TLB miss (instruction n)
Re-execution of instruction n
TLB miss (instruction n + 1)
Re-execution of instruction n + 1
RIE (instruction n + 2)
Legend:
IF
ID
EX
MA
WB
= Instruction fetch
= Instruction decode
= Instruction execution
= Memory access
= Write back
IF
ID
IF
TLB miss (instruction access)
EX
ID
IF
MA
EX
Program Order:
TLB miss (data access)
ID
RIE (reserved instruction exception)
WB
MA
EX
1
2
3
WB
MA
WB