HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 586

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 19 A/D Converter (ADC)
19.3.3
ADCR is an 8-bit read/write register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'07 by a reset and in standby mode.
19.4
ADDRA to ADDRD are 16-bit registers, but they are connected to the bus master by the upper 8
bits of the 16-bit peripheral data bus. Therefore, although the upper byte can be accessed directly
by the bus master, the lower byte is read through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the bus master and the lower-byte value is transferred into TEMP. Next,
when the lower byte is read, the TEMP contents are transferred to the bus master.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, the read value is not guaranteed.
Rev. 5.00 May 29, 2006 page 536 of 698
REJ09B0146-0500
Bit
7
6
5
4, 3
2 to 0
A/D Control Register (ADCR)
Bus Master Interface
Bit Name
TRGE1
TRGE0
SCN
—
—
Initial Value
0
0
0
All 0
All 1
R/W
R/W
R/W
R/W
R/W
R
Description
Trigger Enable
Enables or disables external triggering of A/D
conversion.
00: When an external trigger is input, the A/D
01: The same as above
10: The same as above
11: The A/D conversion starts at the falling edge of
Scan Mode
Selects multi mode or scan mode when the MULTI
bit is set to 1. See the description of bit 4 in 19.3.2,
A/D Control/Status Register (ADCSR).
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
These bits are always read as 1. The write value
should always be 0.
conversion does not start
an input signal from the external trigger pin
(ADTRG).