HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 500

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
Bit
6
5
4
Rev. 5.00 May 29, 2006 page 450 of 698
REJ09B0146-0500
Bit Name
RIE
TE
RE
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Receive Interrupt Enable
Enables or disables the receive-data-full (RXI) and receive-
error (ERI) interrupts requested when the serial receive
data is transferred from the SCRSR2 to SCFRDR2, when
the quantity of data in the SCFRDR2 becomes more than
the specified number of receive triggers, and when the
RDRF flag of SCSSR2 is set to1.
0: Receive-data-full interrupt (RXI), receive-error interrupt
1: Receive-data-full interrupt (RXI) and receive-error
Transmit Enable
Enables or disables the SCIF serial transmitter.
0: Transmitter disabled.
1: Transmitter enabled.
Receive Enable
Enables or disables the SCIF serial receiver.
0: Receiver disabled.
1: Receiver enabled.
(ERI), and receive break interrupt (BRI) requests are
disabled.
Note: RXI and ERI interrupt requests can be cleared by
reading the DR, ER, or RDF flag after it has been set to
1, then clearing the flag to 0, or by clearing RIE to 0. At
RDF, read 1 from the RDF flag and clear it to 0, after
reading the received data from SCFRDR2 until the
quantity of received data becomes less than the
specified number of the receive triggers.
interrupt (ERI) requests are enabled.
Note: Serial transmission starts after writing of transmit
data into the SCFTDR2. Select the transmit format in the
SCSMR2 and SCFCR2 and reset the TFIFO before
setting TE to 1.
Note: Clearing RE to 0 does not affect the receive flags
(DR, ER, BRK, FER and PER). These flags retain their
previous values.
Note: Serial reception starts when a start bit is detected.
Select the receive format in the SCSMR2 before setting
RE to 1.