HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 370

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 11 Watchdog Timer (WDT)
11.3.2
To change the frequency used by the PLL, use the WDT. When changing the frequency only by
switching the divider, do not use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
2. Set the type of count clock used in the CKS2 to CKS0 bits of WTCSR and the initial values for
3. When the frequency control register (FRQCR) is written, the clock stops and the processor
4. When the WDT count overflows, the CPG resumes supplying the clock and the processor
5. The counter stops at the values H'00 to H'01. The stop value depends on the clock ratio.
6. Confirm that the value of WTCNT is H’00 before writing WTCNT, when WTCNT is written
11.3.3
1. Set the WT/IT bit in the WTCSR register to 1, set the reset type in the RSTS bit, set the type of
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent
4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the
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REJ09B0146-0500
is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
enters standby mode temporarily. The WDT starts counting.
resumes operation. The WOVF flag in WTCSR is not set when this happens.
after the frequency change.
count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT
counter.
the counter from overflowing.
type of reset specified by the RSTS bit. The counter then resumes counting.
When a reset occurs, and a high level is output from the STATUS0 and STATUS1 pins. The
signal output period is about one cycle of the count clock for power-on reset, and about five
cycles of the peripheral clock for manual reset.
Changing the Frequency
Using Watchdog Timer Mode