HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 132

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Exception Processing
4.1.2
The reset vector address is fixed at H'A0000000. The other three events are assigned offsets from
the vector base address by software. Translation look-aside buffer (TLB) miss exceptions have an
offset from the vector base address of H'00000400. The vector address offset for general exception
events other than TLB miss exceptions is H'00000100. The interrupt vector address offset is
H'00000600. The vector base address is loaded into the vector base register (VBR) by software.
The vector base address should reside in P1 or P2 fixed physical address space. Figure 4.1 shows
the relationship between the vector base address, the vector offset, and the vector table.
In table 4.1, exceptions and their vector addresses are listed by exception type, instruction
completion state, relative acceptance priority, relative order of occurrence within an instruction
execution sequence and vector address for exceptions and their vector addresses.
Table 4.1
Exception
Type
Reset
General
exception
events
Rev. 5.00 May 29, 2006 page 82 of 698
REJ09B0146-0500
Exception Processing Vector Addresses
Current
Instruction
Aborted
Aborted
and retried
Exception Event Vectors
(Vector base address)
VBR
Power-on
Manual reset
H-UDI reset
CPU Address error
(instruction access)
TLB miss
(instruction access)
TLB invalid (instruction
access)
Exception Event
Figure 4.1 Vector Addresses
+ Vector offset
H'A000 0000
Priority *
1
1
1
2
2
2
1
Exception
Order
—
—
—
1
2
3
Vector address
Vector
Address
H'A00000000
H'A00000000
H'A00000000
—
—
—
Vector
Offset
—
—
—
H'00000100
H'00000400
H'00000100