HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 213

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The bus state controller (BSC) divides physical address space and output control signals for
various types of memory and bus interface specifications. BSC functions enable this LSI to link
directly with DRAM, synchronous DRAM, SRAM, ROM, and other memory storage devices
without an external circuit. The BSC also allows direct connection to PCMCIA interfaces,
simplifying system design and allowing high-speed data transfers in a compact system.
Figure 8.1 shows the block diagram of the BSC.
8.1
The BSC has the following features:
Physical address space is divided into six areas
Direct interface to synchronous DRAM (except when clock ratio becomes I :B = 1:1)
Burst ROM interface
PCMCIA interface
A maximum 64 Mbytes for each of the six areas, 0, 2 to 6
Area bus width can be selected by register (area 0 is set by external pin)
Wait states can be inserted using the WAIT pin
Wait state insertion can be controlled through software. Register settings can be used to
specify the insertion of 1 to 10 cycles independently for each area (1 to 38 cycles for areas
5 and 6 and the PCMCIAT interface only)
The type of memory connected can be specified for each area, and control signals are
output for direct memory connection
Wait cycles are automatically inserted to avoid data bus conflict for continuous memory
accesses to different areas or writes directly following reads of the same area
Multiplexes row/column addresses according to synchronous DRAM capacity
Supports burst operation
Supports bank active mode
Has both auto-refresh and self-refresh functions
Controls timing of synchronous DRAM direct-connection control signals according to
register setting
Insertion of wait states controllable through software
Register setting control of burst transfers
Insertion of wait states controllable through software
Feature
Section 8 Bus State Controller (BSC)
Rev. 5.00 May 29, 2006 page 163 of 698
Section 8 Bus State Controller (BSC)
REJ09B0146-0500