HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 17

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
9.6.1 Example of
DMA Transfer between
A/D Converter and
External Memory
(Address Reload on)
Table 9.7 Values in
the DMAC after the
Fourth Transfer Ends
9.7 Cautions
Section 10 Clock
Pulse Generator
(CPG)
10.1 Feature
Page
299
301,
302
303 to
305,
309 to
312
305
Revision (See Manual for Details)
Table amended
Description added
13. When the DMAC transfers data under conditions (1) or (2)
below, the CPU may fetch an unexpected instruction, resulting
in program runaway, or the DMA may transfer the wrong data.
(1) At wake-up from the sleep mode when operating with a
clock ratio for I :B of other than 1:1.
(2) The internal clock frequency division ratio bits (IFC[2:0]) in
the frequency control register (FRQCR) are modified.
Note that no problem occurs if the clock ratio for I :B is 1:1
after modification of the bits. Furthermore, no problem occurs if
the frequency multiplication ratio bits (STC[2:0]) are modified at
the same time as IFC[2:0].
These problems may be avoided by either of the following
measures.
• Do not use the DMAC when in sleep mode, or set the clock
ratio for I :B to 1:1 before entering sleep mode.
• Do not use the DMAC when modifying only the internal clock
frequency division ratio bits (IFC[2:0]) to produce a clock ratio
for I :B of other than 1:1.
(Before) Internal clock
1. PLL Circuit 1: PLL circuit 1 doubles, triples, quadruples, or
leaves unchanged the input clock frequency from the CKIO pin
or PLL circuit 2.
Description amended
Items
SAR_2
DAR_2
DMATCR_2
Address reload on
H'04000080
H'003FFFF0
H'0000007C
Rev. 5.00 May 29, 2006 page xv of xlviii
(After) CPU clock
Address reload off
H'04000090
H'003FFFF0
H'0000007C