HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 156

IC SUPERH MPU ROMLESS 176LQFP

HD6417706F133

Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417706F133

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Section 5 Cache
5.3.2
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The
LRU is updated.
Read Miss: An external bus cycle starts and the entry is updated. The way replaced is shown in
table 5.3. Entries are updated in 16-byte units. When the desired instruction or data that caused the
miss is loaded from external memory to the cache, the instruction or data is transferred to the CPU
in parallel with being loaded to the cache. When it is loaded in the cache, the U bit is cleared to 0
and the V bit is set to 1.
Rev. 5.00 May 29, 2006 page 106 of 698
REJ09B0146-0500
Legend:
CMP0: Comparison circuit 0
CMP1: Comparison circuit 1
CMP2: Comparison circuit 2
CMP3: Comparison circuit 3
31
Virtual address
MMU
Read Access
Physical address
Entry selection
Figure 5.2 Cache Search Scheme (Normal Mode)
12 11
255
CMP0 CMP1 CMP2 CMP3
0
1
V U Tag address
Hit signal 1
4 3 2 1 0
Ways 0 to 3
Longword (LW) selection
LW0
LW1
LW2
Ways 0 to 3
LW3

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