HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 159

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 5 Cache
bit specified in the data field are written to. However, when 0 is written to the V bit, 0 must also
be written to the U bit of that entry.
Address Array Write (with associative operation): When writing while the associative bit (bit
A) is 1, the addresses of four entries selected by the entry addresses are compared to the tag
addresses specified in the data field. As a result of the comparison, U bit and V bit specified in the
data field are written to the entry for the hit way. Note however, that the tag address and LRU bits
are not changed. When no ways are hit, nothing is written to the address array and no operation
occurs. This operation is used to invalidate a specific entry of the cache. When the U bit of the hit
entry is 1, write back is occurs. However, when 0 is written to the V bit, 0 must also be written to
the U bit of that entry.
5.4.2
Data Array
The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit
address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified.
The address field specifies information for selecting the entry to be accessed; the data field
specifies the longword data to be written to the data array.
In the address field, specify the entry address for selecting the entry (bits 11 to 4), L indicating the
longword position within the (16-byte) line (bits 3 and 2: 00 is longword 0, 01 is longword 1, 10 is
longword 2, and 11 is longword 3), W for selecting the way (bits 13 and 12: 00 is way 0, 01 is way
1, 10 is way 2, and 11 is way 3), and H'F1 to indicate data array access (bits 31 to 24).
The access size of the data array is fixed at longword, so 00 should be specified to bits 1 and 0 in
the address field.
The following two operations are enabled for data array. However, information of the address
array is not changed by the following operations.
Data Array Read: Reads data specified by L (bits 3 and 2) in the address field from the entry
specified by the entry address and the way number.
Data Array Write: Writes a longword data specified by the data field to the position specified by
L (bits 3 and 2) in the address field from the entry specified by the entry address and the way
number.
Rev. 5.00 May 29, 2006 page 109 of 698
REJ09B0146-0500