EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1002

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–44
Table 1–13. MegaWizard Plug-In Manager Options (Rate Match/Byte Order Screen) (Part 1 of 3)
Stratix IV Device Handbook Volume 3
Enable rate match FIFO.
What is the 20-bit rate match
pattern1? (usually used for +ve
disparity pattern)
What is the 20-bit rate match
pattern2? (usually used for -ve
disparity pattern)
Create the rx_rmfifofull port to
indicate when the rate match FIFO is
full.
ALTGX Setting
Table 1–13
MegaWizard Plug-In Manager for your ALTGX custom megafunction variation.
lists the available options on the Rate Match/Byte Order screen of the
This option enables the rate match (clock rate
compensation) FIFO. The rate match block consists
of a 20-word deep FIFO. Depending on the PPM
difference, the rate match FIFO controls insertion and
deletion of skip characters based on the 20-bit rate
match pattern you enter in the What is the 20-bit rate
match pattern1? and What is the 20-bit rate match
pattern2? options.
To enable this block:
■
■
The rate match block is capable of compensating up
to ±300 PPM difference between the upstream
transmitter clock and the local receiver’s input
reference clock.
Enter a 10-bit skip pattern and a 10-bit control
pattern. In the skip pattern field, you must choose a
10-bit code group that has neutral disparity. When
the rate matcher receives the 10-bit control pattern
followed by the 10-bit skip pattern, it inserts or
deletes the 10-bit skip pattern as necessary to avoid
rate match FIFO overflow or underflow conditions.
Enter a 10-bit skip pattern and a 10-bit control
pattern. In the skip pattern field, you must choose a
10-bit code group that has neutral disparity. When
the rate matcher receives the 10-bit control pattern
followed by the 10-bit skip pattern, it inserts or
deletes the 10-bit skip pattern as necessary to avoid
rate match FIFO overflow or underflow conditions.
This option creates the output port rx_rmfifofull
when you enable the Enable Rate Match FIFO option.
It is a status flag that the rate match block forwards
to the FPGA fabric. It indicates when the rate match
FIFO block is full (20 words). This signal remains
high as long as the FIFO is full. It is asynchronous to
the receiver data path.
(1)
(1)
The transceiver channel must have both the
transmitter and the receiver channels instantiated.
You must select the Receiver and Transmitter
option in the What is the operation mode? field in
the General screen.
You must also enable the 8B/10B encoder/decoder
in the 8B10B screen.
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the
Architecture In Stratix IV
Devices
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the
Architecture in Stratix IV
Devices
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the
Architecture in Stratix IV
Devices
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the
Architecture in Stratix IV
Devices
February 2011 Altera Corporation
chapter.
chapter.
chapter.
chapter.
Reference
Protocol Settings
Transceiver
Transceiver
Transceiver
Transceiver