EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 599

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
PCS code groups are sent via PCS ordered sets. PCS ordered sets consist of
combinations of special and data code groups defined as a column of code groups.
These ordered sets are composed of four code groups beginning in lane 0.
lists the defined idle ordered sets (||I||) that are used for the self-managed
properties of XAUI.
Table 1–59. Defined Idle Ordered Set
Stratix IV GX and GT transceivers configured in XAUI mode provide the following
protocol features:
■
■
■
■
■
■
XGMII-to-PCS code conversion at the transmitter
PCS-to-XGMII code conversion at the receiver
8B/10B encoding and decoding
IEEE P802.3ae-compliant synchronization state machine
±100 PPM clock rate compensation
Channel deskew of four lanes of the XAUI link
Code
||R||
||K||
||A||
||I||
Synchronization column
Align column
Skip column
Ordered Set
Idle
Code Groups
Number of
4
4
4
Stratix IV Device Handbook Volume 2: Transceivers
/K28.5/K28.5/K28.5/K28.5/
/K28.0/K28.0/K28.0/K28.0/
/K28.3/K28.3/K28.3/K28.3/
Substitute for XGMII Idle
Encoding
Table 1–59
1–155