EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 203

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
February 2011 Altera Corporation
LVDS Input OCT (R
Summary of OCT Assignments
f
Stratix IV devices support OCT for differential LVDS input buffers with a nominal
resistance value of 100 Ω , as shown in
in row I/O banks when both the V
do not support OCT R
PLL_L[1,4]_CLK[p,n], and PLL_R[1,4]_CLK[p,n] on the row I/O banks of Stratix IV
devices do not support R
Figure 6–22. Differential Input OCT
For more information about differential on-chip termination, refer to the
Differential I/O Interfaces and DPA in Stratix IV Devices
Table 6–9
Table 6–9. Summary of OCT Assignments in the Quartus II Software
Input Termination
Output Termination
Note to
(1) You can enable differential OCT R
Assignment Name
Table
lists the OCT assignments for the Quartus II software version 9.1 and later.
D
6–9:
)
Transmitter
D.
Parallel 50 Ω with calibration
Differential
Series 25 Ω without calibration
Series 50 Ω without calibration
Series 25 Ω with calibration
Series 40 Ω with calibration
Series 50 Ω with calibration
Series 60 Ω with calibration
Dedicated clock input pairs CLK[1,3,8,10][p,n],
D
termination.
D
in row I/O banks when both V
Value
CCIO
Figure
Z
Z
O
O
and V
= 50 Ω
= 50 Ω
6–22. Differential OCT R
CCPD
is set to 2.5 V. Column I/O banks
CCIO
Input buffers for single-ended and
differential HSTL/SSTL standards
Input buffers for LVDS receivers on
row I/O banks
Output buffers for single-ended
LVTTL/LVCMOS and HSTL/SSTL
standards as well as differential
HSTL/SSTL standards
chapter.
and V
CCPD
100 Ω
Stratix IV Device Handbook Volume 1
are set to 2.5 V.
Applies To
Receiver
(1)
D
can be enabled
High Speed
6–31