EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 540

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–96
Stratix IV Device Handbook Volume 2: Transceivers
1
Table 1–35
Table 1–35. Double Width Functional Modes for the Byte Ordering Block
For more information about configurations that allow the byte ordering block in the
receiver datapath, refer to
In Basic double-width modes, you can program a custom byte ordering pattern and
byte ordering PAD pattern in the ALTGX MegaWizard Plug-In Manager.
lists the byte ordering pattern length allowed in Basic double-width mode.
Table 1–36. Byte Ordering Pattern Length in Basic Double-Width Mode
Basic double-width mode with:
Basic double-width mode with:
Basic double-width mode with:
Basic double-width mode with:
■
■
■
Basic double-width mode with:
■
■
■
Basic double-width mode with:
■
■
■
Note to
(1) The 18-bit byte ordering pattern D[17:0] consists of MSByte D[17:9] and LSByte D[8:0]; D[17] corresponds
32-bit FPGA fabric-transceiver interface
No 8B/10B decoder (16-bit PMA-PCS interface)
Word aligner in manual alignment mode
32-bit FPGA fabric-transceiver interface
8B/10B decoder (20-bit PMA-PCS interface)
Word aligner in manual alignment mode
40-bit FPGA fabric-transceiver interface
No 8B/10B decoder (20-bit PMA-PCS interface)
Word aligner in manual alignment mode
Byte Ordering Block in Double-Width Modes
to rx_ctrldetect[1] and D[16:9] corresponds to rx_dataout[15:8]. Similarly, D[9] corresponds to
rx_ctrldetect[0] and D[7:0] corresponds to rx_dataout[7:0].
Table
Functional Modes
lists the double-width byte ordering block functional modes.
1–36:
Functional Mode
“Basic Double-Width Mode Configurations” on page
■
■
■
■
■
■
■
■
■
32-bit FPGA fabric-transceiver interface
No 8B/10B decoder (16-bit PMA-PCS interface)
Word aligner in manual alignment mode
32-bit FPGA fabric-transceiver interface
8B/10B decoder (20-bit PMA-PCS interface)
Word aligner in manual alignment mode
40-bit FPGA fabric-transceiver interface
No 8B/10B decoder (20-bit PMA-PCS interface)
Word aligner in manual alignment mode
Chapter 1: Transceiver Architecture in Stratix IV Devices
18 bits, 9 bits
Pattern Length
20 bits, 10 bits
Byte Ordering
16 bits, 8 bits
Descriptions
(1)
February 2011 Altera Corporation
Transceiver Block Architecture
Byte Ordering PAD
Pattern Length
10 bits
Table 1–36
8 bits
9 bits
1–117.