EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 60
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
- Current page: 60 of 1154
- Download datasheet (32Mb)
3–4
Figure 3–1. Byte Enable Functional Waveform
Stratix IV Device Handbook Volume 1
current data: q (asynch)
don't care: q (asynch)
contents at a0
contents at a1
contents at a2
Packed Mode Support
address
byteena
inclock
1
wren
data
You cannot use the byte enable feature when using the error correction coding (ECC)
feature on M144K blocks.
Figure 3–1
control the operations of the RAM blocks.
When a byte-enable bit is de-asserted during a write cycle, the corresponding data
byte output can appear as either a “don’t care” value or the current data at that
location. The output value for the masked byte is controllable using the Quartus II
software. When a byte-enable bit is asserted during a write cycle, the corresponding
data byte output also depends on the setting chosen in the Quartus II software.
Stratix IV M9K and M144K blocks support packed mode. The packed mode feature
packs two independent single-port RAMs into one memory block. The Quartus II
software automatically implements packed mode where appropriate by placing the
physical RAM block into true dual-port mode and using the MSB of the address to
distinguish between the two logical RAMs. The size of each independent single-port
RAM must not exceed half of the target block size.
XXXX
XX
an
FFFF
doutn
doutn
FFFF
shows how the write enable (wren) and byte enable (byteena) signals
10
a0
FFFF
ABXX
ABFF
ABCD
01
a1
XXCD
FFCD
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
11
a2
ABCD
ABCD
ABFF
a0
FFCD
ABFF
ABFF
ABCD
a1
February 2011 Altera Corporation
XXXX
XX
FFCD
FFCD
a2
ABCD
ABCD
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