EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 455
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EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Channel Locations
February 2011 Altera Corporation
Figure 1–6
the EP4S40G5H40 Stratix IV GT devices.
Figure 1–6. Transceiver Channel, PLL, and PCIe Hard IP Block Locations in EP4S40G5H40
Stratix IV GT Devices
Note to
(1) If you are using the PCIe hard IP block, the EP4S40G2F40 device is not able to migrate to the EP4S40G5H40 device.
Figure
EP4S40G5H40
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
shows the transceiver channel, PLL, and PCIe hard IP block locations for
10G Channel 3
10G Channel 2
10G Channel 1
10G Channel 0
CMU Channel 1
CMU Channel 0
10G Channel 3
10G Channel 2
CMU Channel 1
CMU Channel 0
1–6:
8G Channel 1
8G Channel 0
ATX PLL (10G)
CMU Channel 1
CMU Channel 0
8G Channel 1
8G Channel 0
ATX PLL (6G)
8G Channel 3
8G Channel 2
(Note 1)
Stratix IV Device Handbook Volume 2: Transceivers
Transceiver Block GXBR2
Transceiver Block GXBR1
Transceiver Block GXBR0
10G Channel 3
10G Channel 2
10G Channel 1
10G Channel 0
10G Channel 3
10G Channel 2
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
8G Channel 1
8G Channel 0
CMU Channel 1
CMU Channel 0
ATX PLL (10G)
8G Channel 1
8G Channel 0
8G Channel 3
8G Channel 2
ATX PLL (6G)
1–11
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