EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 898

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

5–52
Stratix IV Device Handbook Volume 2: Transceivers
The PLL logical reference index of additional PLLs outside the transceiver block can
only be 2 or 3.
■
■
For more information about the PLL logical reference index of CMU PLLs within the
same transceiver block, refer to
PLL” on page
ALTGX_RECONFIG MegaWizard Plug-In Manager Setup for Channel Reconfiguration with
Transmitter PLL Select Mode
For more information, refer to the
Manager Setup for Channel and CMU PLL Reconfiguration Mode” on page
Channel Reconfiguration with Transmitter PLL Select Operation
Read transactions are not allowed in this mode.
Figure 5–25
transceiver channel. The .mif write transaction in channel reconfiguration with
transmitter PLL select mode remains the same except for the
reconfig_mode_sel[2:0] value and the difference in the number of .mif words used.
In this example, the transceiver channel is configured in Receiver and Transmitter
configuration. Therefore, the .mif size is 8.
You can optionally choose to trigger write_all once by selecting the continuous write
operation in the ALTGX_RECONFIG MegaWizard Plug-In Manager. The Quartus II
software then continuously writes all the words required for reconfiguration.
When you enable the Use central clock divider to drive the transmitter channels
using ×4/×N lines option for an additional PLL, you can only select between 2 or 3
as the PLL logical reference index.
When you disable the Use central clock divider to drive the transmitter channels
using ×4/×N lines option for an additional PLL, the additional PLL is one of the
CMU PLLs within the same transceiver block. Therefore, the PLL logical reference
index is either 0 or 1.
Selecting the PLL Logical Reference Index for Additional PLLs
shows a .mif write transaction when dynamically reconfiguring a
5–29.
“Selecting the Logical Reference Index of the CMU
“ALTGX_RECONFIG MegaWizard Plug-In
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
5–46.