EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 582

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–138
Stratix IV Device Handbook Volume 2: Transceivers
1
1
Fast Recovery Mode
The PCIe Base specification fast training sequences (FTS) are used for bit and byte
synchronization to transition from L0s to L0 (PCIe P0s to P0) power states. When
transitioning from the L0s to L0 power state, the PCIe Base Specification requires the
physical layer device to acquire bit and byte synchronization after receiving a
maximum of 255 FTS (~4 us at Gen1 data rate and ~2 us at Gen2 data rate).
If you have configured the Stratix IV GX and GT receiver CDR in Automatic Lock
mode, the receiver cannot meet the PCIe specification of acquiring bit and byte
synchronization within 4 μs (Gen1 data rate) or 2 μs (Gen2 data rate) due to the signal
detect and PPM detector time. To meet this specification, each Stratix IV GX and GT
transceiver has a built-in Fast Recovery circuitry that you can optionally enable.
To enable the Fast Recovery circuitry, select the Enable fast recovery mode option in
the ALTGX MegaWizard Plug-In Manager.
If you enable the Fast Recovery mode option, the Fast Recovery circuitry controls the
receiver CDR rx_locktorefclk and rx_locktodata signals to force the receiver CDR
in LTR or LTD mode. It relies on the Electrical Idle Ordered Sets (EIOS), N_FTS
sequences received in the L0 power state, and the signal detect signal from the
receiver input buffer to control the receiver CDR lock mode.
The Fast Recovery circuitry is self-operational and does not require control inputs
from you. When enabled, the rx_locktorefclk and rx_locktodata ports are not
available in the ALTGX MegaWizard Plug-In Manager.
Electrical Idle Inference
The PCIe protocol allows inferring the electrical idle condition at the receiver instead
of detecting the electrical idle condition using analog circuitry. Clause 4.2.4.3 in the
PCIe Base Specification 2.0 specifies conditions to infer electrical idle at the receiver in
various substates of the LTSSM state machine.
In all PCIe modes (×1, ×4, and ×8), each receiver channel PCS has an optional
Electrical Idle Inference module designed to implement the electrical idle inference
conditions specified in the PCIe Base Specification 2.0. You can enable the Electrical
Idle Inference module by selecting the Enable electrical idle inference functionality
option in the ALTGX MegaWizard Plug-In manager.
If enabled, this module infers electrical idle depending on the logic level driven on the
rx_elecidleinfersel[2:0] input signal. The Electrical Idle Inference module in each
receiver channel indicates whether the electrical idle condition is inferred or not on
the pipeelecidle signal of that channel. The Electrical Idle Interface module drives
the pipeelecidle signal high if it infers an electrical idle condition; otherwise, it
drives it low.
Chapter 1: Transceiver Architecture in Stratix IV Devices
February 2011 Altera Corporation
Transceiver Block Architecture