EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1018
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EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
EP4SE530H40I3
Manufacturer:
ALTERA
Quantity:
325
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
SHARP
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Part Number:
EP4SE530H40I3N
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ALTERA
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490
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Document Revision History
Table 1–19. Document Revision History
Stratix IV Device Handbook Volume 3
February 2011
November 2009
June 2009
March 2009
November 2008
June 2008
May 2008
Date
Version
Table 1–19
4.0
2.0
4.1
3.1
3.0
1.1
1.0
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Minor text edit.
Initial release.
Updated
Updated chapter title.
Minor text edits.
Applied new template.
Added Deterministic Latency protocol information.
Added AEQ information.
Updated PLL setting information.
Consolidated Parameter Settings information (Table 1–1 to Table 1–6).
Consolidated Reconfiguration Settings information (Table 1–7 to Table 1–9).
Consolidated Protocol Settings information (Table 1–10 to Table 1–18).
Minor text edits.
Updated Table 1–9, Table 1–29 and Table 1–35.
Updated Figure 1–10.
Added introductory sentences to improve search ability.
Minor text edits.
Updated the figures to match the software changes.
Removed the 'Deterministic Latency' subprotocol from Basic functional mode.
Removed the various clock frequencies from the Reconfig Clks screen for all the
applicable functional modes.
Updated Table 1–1, Table 1–6, and Table 1–11.
Updated Figure 1–8.
Added Reconfig Clks and Reconfig 2 sections.
Added the “Use ATX Transmitter PLL” setting.
Changed the “Which device speed grade will you be using?” setting to the “Which device
variation will you be using” setting.
lists the revision history for this chapter.
Table
1–1,
Table
1–3,
Table
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
1–7, and
Changes
Table
1–17.
February 2011 Altera Corporation
Document Revision History
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