EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 104

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

4–24
Figure 4–15. Loopback Mode for a Half DSP Block
Note to
(1) Block output for accumulator overflow and saturate overflow.
Stratix IV Device Handbook Volume 1
Figure
dataa_0[17..0]
datab_0[17..0]
dataa_1[17..0]
datab_1[17..0]
18 x 18 Complex Multiply
4–15:
zero_loopback
You can configure the DSP block to implement complex multipliers using
two-multiplier adder mode. A single half DSP block can implement one 18-bit
complex multiplier.
Equation 4–4
Equation 4–4. Complex Multiplication Equation
Half-DSP Block
loopback
clock[3..0]
ena[3..0]
aclr[3..0]
shows a complex multiplication.
(a + jb) × (c + jd) = ((a × c) – (b × d)) + j((a × d) + (b × c))
output_saturate
+
output_round
signa
signb
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
February 2011 Altera Corporation
overflow (1)
result[ ]