EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 573
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Price
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Manufacturer:
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EP4SE530H40I3N
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490
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–106. Stratix IV GX and GT Transceivers in PCIe Functional Mode
February 2011 Altera Corporation
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
Interface Frequency
PCS-FPGA Fabric
PCS-FPGA Fabric
TX PCS Latency
Interface Frequency
RX PCS Latency
Rate Match FIFO
PCS-hardIP or
8B/10B Encoder/
Functional Mode
Channel Bonding
Interface Width
PCS-hardIP or
Interface Width
Interface Width
Byte SerDes
PCI Express
Word Aligner
Data Rate
PMA-PCS
PMA-PCS
Functional
Decoder
(Pattern)
hardIP
Modes
Figure 1–106
PCIe functional mode.
8-bit
Single
Width
10-bit
Enabled
250 MHz
Disabled
20 - 24
8-Bit
5 - 6
Basic
16-bit
shows the Stratix IV GX and GT transceiver configurations allowed in
Double
Width
(/K28.5+/,/K28.5-/)
Synchronization
State Machine
Stratix IV GX and GT Configurations
2.5 Gbps
x1, x4, x8
Automatic
Enabled
Enabled
(Gen1)
20-bit
10-Bit
250 MHz
Disabled
20 - 24
5 - 6
8-Bit
PIPE
10-bit
Disabled
10-bit
XAUI
125 MHz
Enabled
4 - 5.5
16-Bit
11.5 -
14.5
GIGE
10-bit
PIPE
Protocol
SRIO
10-bit
SONET
Stratix IV Device Handbook Volume 2: Transceivers
/SDH
8-bit
Enabled
Disabled
500 MHz
20 - 24
8-Bit
5 - 6
16-bit
(OIF)
CEI
10-bit
(/K28.5+/,/K28.5-/)
SDI
Synchronization
State Machine
Automatic
x1, x4, x8
Enabled
Enabled
5 Gbps
(Gen2)
10-Bit
10-Bit
Deterministic
Latency
20-Bit
Disabled
250 MHz
Enabled
4 - 5.5
16-Bit
11.5 -
14.5
1–129
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