EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 19
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SE230F29C3N PDF datasheet #6
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Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
February 2011 Altera Corporation
Stratix IV GT Devices
1
1
Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device:
■
■
The actual number of transceiver channels per device varies with device selection. For
more information about the exact transceiver count in each device, refer to
on page
For more information about Stratix IV GT devices and transceiver architecture, refer
to the
Figure 1–3
Figure 1–3. Stratix IV GT Chip View
Note to
(1) Resource counts vary with device selection, package selection, or both.
Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA
circuitry and support data rates between 600 Mbps and 11.3 Gbps
The remaining 16 transceiver channels have dedicated PMA-only circuitry and
support data rates between 600 Mbps and 6.5 Gbps
Figure
Transceiver Architecture in Stratix IV Devices
1–16.
shows a high-level Stratix IV GT chip view.
1–3:
General Purpose I/O and
PLL
PLL
PLL
PLL
with DPA and Soft CDR
High-Speed LVDS I/O
Transceiver Block
General Purpose
I/O and Memory
General Purpose
I/O and Memory
Interface
Interface
(Note 1)
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
FPGA Fabric
PLL PLL
PLL PLL
600 Mbps-11.3 Gbps CDR-based Transceiver
General Purpose I/O and up to 1.6 Gbps
LVDS interface with DPA and Soft-CDR
chapter.
General Purpose
I/O and Memory
General Purpose
I/O and Memory
Interface
Interface
Stratix IV Device Handbook Volume 1
PLL
PLL
PLL
PLL
Table 1–7
1–5
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