EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1023

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Architecture
February 2011 Altera Corporation
Clocking
f
f
The Stratix IV GX transceiver is clocked by various input reference clocks, for
example:
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Identify the transceiver channels input reference clock sources, for example:
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For transceiver-FPGA interface clocking:
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For information about transceiver specifications, refer to the
Characteristics for Stratix IV Devices
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For information about transceiver clocking, refer to the
Stratix IV Devices
After you identify the required transceiver parameters, start the implementation and
integration phase.
Dedicated transceiver reference clock (refclk) pins. Altera recommends using
refclk pins whenever possible because the refclk pins yield reduced jitter on the
transmitted data.
Clock sources connected to global clock lines.
Clock outputs from the phase-locked loops (PLLs) in the FPGA fabric.
Ensure that your selected device has the required number of input reference clock
resources to implement your design.
Ensure that the transceiver clock input supports the required I/O standards.
Ensure that the clocking restrictions work with your selected device:
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Ensure that the transceiver-FPGA interface clock frequency limits meet your
system requirements.
Identify the clocking scheme to clock the transceiver data to the logic in the FPGA
fabric. For example, if your design has multiple transceiver channels that run at
the same data rate and are connected to the one upstream link, you might be able
to use a single transceiver-FPGA clock to provide clocks to the transceiver data
path, which can conserve clock routing resources.
If you are using Basic (PMA direct) mode, determine whether you require a
left/right PLL to provide phase shifted clocks to the FPGA fabric. The left/right
PLL clocks the data received and transmitted between the transceiver and the
FPGA fabric interface and may be required to meet the timing requirements of the
data transfer.
Check whether the allowed frequencies for the transceiver input reference
clocks meet your system requirements.
If you use the PLL cascade clock, understand its restrictions.
If you are using the auxiliary transmit (ATX) PLL, understand the
recommendations for the input reference clock sources and the restrictions on
data rate ranges supported by the ATX PLL.
chapter.
chapter.
Transceiver Clocking in
Stratix IV Device Handbook Volume 3
DC and Switching
2–5