EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 558
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
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Manufacturer:
ALTERA
Quantity:
325
Company:
Part Number:
EP4SE530H40I3N
Manufacturer:
SHARP
Quantity:
1 200
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Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA
Quantity:
490
Part Number:
EP4SE530H40I3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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1–114
Figure 1–95. Transceiver Configurations in Basic Single-Width Mode with an 8-Bit PMA-PCS Interface for Stratix IV GT
Devices
Note to
(1) The maximum data rate specification shown in
Stratix IV Device Handbook Volume 2: Transceivers
other speed grades offered, refer to the
Figure
(1)
FPGA Fabric
Interface Frequency
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
(1)
Interface Clock Cycles)
Interface Clock Cycles)
Interface Frequency
Interface Frequency
TX PCS Latency
RX PCS Latency
Data Rate (Gbps)
1–95:
Low-Latency PCS
Channel Bonding
Rate Match FIFO
PMA-PCS/Fabric
Encoder/Decoder
Interface Width
(Pattern Length)
FPGA Fabric-
FPGA Fabric-
Interface Width
Byte Ordering
FPGA Fabric-
Transceiver
Transceiver
Transceiver
Word Aligner
Byte SerDes
Data Rate
PMA-PCS/Fabric
Interface Width
(MHz)
Functional
8B/10B
Modes
8-bit
Single
Width
Disabled
Manual Alignment
195 .3125
10-bit
155.5 –
16-bit
4 - 5.5
7 - 9
DC and Switching Characteristics
Disabled
Disabled
Enabled
(16-bit)
Basic
3.125
0.6 -
16-bit
Enabled
195.3125
4 - 5.5
155.5 –
16-bit
Figure 1–95
7 - 9
Double
Width
Disabled
20-bit
Stratix IV GT Configurations
is valid only for the -2 (fastest) speed grade devices. For data rate specifications for
Disabled
Disabled
Disabled
Enabled
195.3125
Bit-Slip
(16-bit)
4 - 5.5
155.5 –
16-bit
600 Mbps to 3.2 Gbps
3.125
0.6 -
7 - 9
Basic Single Width
8-bit PMA-PCS
Interface Width
x1, x4, x8
chapter.
10-bit
PIPE
Chapter 1: Transceiver Architecture in Stratix IV Devices
10-bit
XAUI
Protocol
SRIO
10-bit
SONET
/SDH
8-bit
16-bit
(OIF)
CEI
February 2011 Altera Corporation
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
0.6 - 3.2
16-bit
4 - 5.5
155.5 -
3 - 4.5
200
Transceiver Block Architecture
10-bit
SDI
10-Bit
Deterministic
Latency
20-Bit
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