EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 499

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
1
1
The feedback path from the CDR VCO to the PD has a /2 divider that is used in PCIe
mode configured at Gen2 (5 Gbps) data rate for the dynamic switch between Gen1
(2.5 Gbps) and Gen2 (5 Gbps) signaling rates. When the PHY-MAC layer instructs a
Gen2-to-Gen1 signaling rateswitch, the /2 divider is enabled. When the PHY-MAC
layer instructs a Gen1-to-Gen2 signaling rateswitch, the /2 divider is disabled. For
more information about the PCIe signaling rateswitch, refer to
Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signaling Rate” on page
The /2 divider in the receiver CDR between the VCO and the PD is disabled in all
other functional modes.
The LTR/LTD controller controls whether the CDR is in LTR or LTD mode. You can
configure the LTR/LTD controller either in automatic lock mode or manual lock
mode.
Two optional input ports (rx_locktorefclk and rx_locktodata) allow you to
configure the LTR/LTD controller in either automatic lock mode or manual lock
mode.
LTR/LTD controller lock mode.
Table 1–25. Optional Input Ports and LTR/LTD Controller Lock Mode
If you do not instantiate the optional rx_locktorefclk and rx_locktodata signals, the
Quartus II software automatically configures the LTR/LTD controller in automatic
lock mode.
In automatic lock mode, the LTR/LTD controller initially sets the CDR to lock to the
input reference clock (LTR mode). After the CDR locks to the input reference clock,
the LTR/LTD controller automatically sets it to lock to the incoming serial data (LTD
mode) when the following three conditions are met:
■
■
■
The switch from LTR to LTD mode is indicated by the assertion of the rx_freqlocked
signal.
Signal threshold detection circuitry indicates the presence of valid signal levels at
the receiver input buffer
■
The CDR output clock is within the configured PPM frequency threshold setting
with respect to the input reference clock (frequency locked)
The CDR output clock and the input reference clock are phase matched within
approximately 0.08 UI (phase locked)
PCIe Clock Switch Circuitry
LTR/LTD Controller
rx_locktorefclk
Table 1–25
Valid for PCIe mode only. This condition is defaulted to true for all other
modes.
Automatic Lock Mode
1
x
0
lists the relationship between these optional input ports and the
rx_locktodata
0
1
0
Stratix IV Device Handbook Volume 2: Transceivers
LTR/LTD Controller Lock Mode
Automatic Lock Mode
Manual – LTR Mode
Manual – LTD Mode
“Dynamic Switch
1–141.
1–55