EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 893
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–22. .mif Write Transaction in Channel and CMU PLL Reconfiguration Mode
Notes to
(1) The logical_channel_address port is set to 2’b01 to reconfigure the second transceiver channel.
(2) The rx_tx_duplex_sel[1:0] port is set to 2’b00 to match the Receiver and Transmitter configuration of the specified transceiver channel.
February 2011 Altera Corporation
logical_channel_address[1:0]
reconfig_address_out[5:0]
Figure
channel_reconfig_done
reconfig_mode_sel[2:0]
rx_tx_duplex_sel[1:0]
reconfig_address_en
reconfig_data[15:0]
5–22:
f
reconfig_clk
write_all
Figure 5–22
reconfiguration mode.
For guidelines regarding re-using .mifs, specifying input reference clocks, or using
logical_tx_pll_sel ports, refer to
For more information about reset, refer to the “Reset Sequence when Using Dynamic
Reconfiguration with the Channel and TX PLL select/reconfig Option” section in the
Reset Control and Power Down in Stratix IV Devices
Channel Reconfiguration with Transmitter PLL Select Mode Details
You can reconfigure the data rate of a transceiver channel by switching between a
maximum of four transmitter PLLs.
You can select between the following transmitter PLLs:
■
■
■
busy
CMU PLLs present in a transceiver block
CMU PLLs present in other transceiver blocks
ATX PLLs outside the transceiver block
shows a .mif write transaction when using channel and CMU PLL
1st 16 bits Don’t care
Addr0
2nd 16 bits
Addr1
3’b101
2’b01
2’b00
“Special Guidelines” on page
Stratix IV Device Handbook Volume 2: Transceivers
chapter.
55th 16 bits
Addr54
Don’t care
5–56.
Addr0
5–47
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