EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 98

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EP4SE530H40I3

Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H40I3

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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4–18
Stratix IV Device Handbook Volume 1
1
Figure 4–10. 9-Bit Independent Multiplier Mode Shown for a Half Block
The multiplier operands can accept signed integers, unsigned integers, or a
combination of both. You can change the signa and signb signals dynamically and
can register the signals in the DSP block. Additionally, the multiplier inputs and
results can be registered independently. You can use the pipeline registers within the
DSP block to pipeline the multiplier result, increasing the performance of the DSP
block.
The rounding and saturation logic unit is supported for 18-bit independent multiplier
mode only.
datab_1[8..0]
dataa_0[8..0]
datab_0[8..0]
dataa_1[8..0]
dataa_2[8..0]
datab_2[8..0]
dataa_3[8..0]
datab_3[8..0]
clock[3..0]
ena[3..0]
aclr[3..0]
9
9
9
9
9
9
9
9
Half-DSP Block
signa
signb
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
February 2011 Altera Corporation
18
18
18
18
result_0[ ]
result_1[ ]
result_2[ ]
result_3[ ]

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