EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 232

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

7–12
Figure 7–7. Number of DQS/DQ Groups per Bank in EP4SGX70 and EP4SGX110 Devices with 24 Transceivers in the
1152-Pin FineLine BGA Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX70 and EP4SGX110 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
Stratix IV Device Handbook Volume 1
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Figure
7–7:
26 User I/Os (5)
26 User I/Os (5)
I/O Bank 1A (3)
I/O Bank 1C (4)
I/O Bank 1C (4)
32 User I/Os
32 User I/Os
x16/x18=0
x16/x18=0
x16/x18=1
x16/x18=1
x8/x9=1
x8/x9=1
x8/x9=2
x8/x9=2
DLL0
DLL1
x4=3
x4=3
x4=4
x4=4
UP
and R
I/O Bank 8A (3)
I/O Bank 3A (3)
(Note
40 User I/Os
40 User I/Os
x16/x18=1
x16/x18=1
DN
x8/x9=3
x8/x9=3
x4=6
x4=6
pins for OCT calibration. If two pins of a ×4 group are used as R
1), (2), (3), (4),
24 User I/Os
EP4SGX70 and EP4SGX110 Devices
I/O Bank 8C
x16/x18=0
I/O Bank 3C
x8/x9=1
24 User I/Os
x16/x18=0
x4=2
x8/x9=1
in the 1152-Pin FineLine BGA
x4=2
(with 24 Transceivers)
UP
(5)
and R
DN
24 User I/Os
I/O Bank 7C
x16/x18=0
24 User I/Os
I/O Bank 4C
x16/x18=0
x8/x9=1
pins, but you cannot use a ×4 group for memory interfaces if two pins
x8/x9=1
x4=3
x4=3
7–26.
Chapter 7: External Memory Interfaces in Stratix IV Devices
I/O Bank 7A (3)
I/O Bank 4A (3)
40 User I/Os
40 User I/Os
x16/x18=1
x16/x18=1
x8/x9=3
x8/x9=3
x4=6
x4=6
UP
and R
February 2011 Altera Corporation
26 User I/Os (5)
26 User I/Os (5)
I/O Bank 6A (3)
I/O Bank 6A (3)
I/O Bank 6C
I/O Bank 6C
32 User I/Os
32 User I/Os
x16/x18=0
x16/x18=0
x16/x18=1
x16/x18=1
x8/x9=1
x8/x9=1
Memory Interfaces Pin Support
DN
x8/x9=2
x8/x9=2
DLL3
x4=3
x4=3
DLL2
x4=4
x4=4
pins for OCT calibration, you
“Combining