EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 520

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–76
Figure 1–58. Deskew FIFO—Lane Skew at the Receiver Input
Stratix IV Device Handbook Volume 2: Transceivers
Lane 0
1
Lane 2
K
Lane 3
Lane 1
Deskew circuitry performs the deskew operation by the XAUI functional mode.
Deskew circuitry consists of:
■
■
Deskew circuitry is only available in XAUI mode.
The deskew FIFO in each channel receives data from its word aligner. The deskew
operation begins only after link synchronization is achieved on all four channels as
indicated by a high level on the rx_syncstatus signal from the word aligner in each
channel. Until the first /A/ code group is received, the deskew FIFO read and write
pointers in each channel are not incremented. After the first /A/ code group is
received, the write pointer starts incrementing for each word received but the read
pointer is frozen. If the /A/ code group is received on each of the four channels
within 10 recovered clock cycles of each other, the read pointer for all four deskew
FIFOs is released simultaneously, aligning all four channels.
Figure 1–58
/A/ code group to align the channels.
After alignment of the first ||A|| column, if three additional aligned ||A||
columns are observed at the output of the deskew FIFOs of the four channels, the
rx_channelaligned signal is asserted high, indicating channel alignment is acquired.
After acquiring channel alignment, if four misaligned ||A|| columns are seen at the
output of the deskew FIFOs in all four channels with no aligned ||A|| columns in
between, the rx_channelaligned signal is de-asserted low, indicating loss-of-channel
alignment.
Lane 0
Lane 1
Lane 2
Lane 3
K
K
A 16-word deep deskew FIFO in each of the four channels
Control logic in the CMU0 channel of the transceiver block that controls the deskew
FIFO write and read operations in each channel
R
K
K
K
K
K
K
K
R
A
K
K
shows lane skew at the receiver input and how the deskew FIFO uses the
K
K
K
K
R
K
R
A
R
R
R
R
R
A
A
K
A
A
A
A
K
K
R
R
K
K
K
K
R
K
R
R
R
R
R
R
K
R
K
R
R
R
R
R
K
K
R
K
Chapter 1: Transceiver Architecture in Stratix IV Devices
K
K
K
K
R
K
K
K
K
K
K
K
R
R
R
K
R
R
R
R
R
K
K
K
K
K
K
R
R
February 2011 Altera Corporation
R
R
R
R
Transceiver Block Architecture
Lane Skew at
Receiver Input
Lanes are
Deskewed by
Lining up
the "Align"/A/,
Code Groups