EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 965
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 4 of 10)
February 2011 Altera Corporation
What is the operation mode?
What is the number of
channels?
ALTGX Setting
Basic
Basic (PMA Direct)
Deterministic Latency
SDI
Serial RapidIO
SONET/SDH
The available operation modes are Receiver only,
Transmitter only, and Receiver and Transmitter.
GIGE
The available operation modes are Transmitter only, and
Receiver and Transmitter.
PCIe
XAUI
Only Receiver and Transmitter mode is allowed.
Basic
Basic (PMA Direct)
Deterministic Latency
SDI
Serial RapidIO
The number of channels required with the same
configuration. This option determines how many
identical channels this ALTGX instance contains.
GIGE
(OIF) CEI PHY Interface
SONET/SDH
This option allows you to select how many channels this
ALTGX instance contains. In these modes, the number of
channels increments by one.
PCIe
This is the number of channels required with the same
configuration.
■
■
XAUI
This option allows you to select how many identical
channels this ALTGX instance contains. In XAUI mode,
the number of channels increments by 4.
In a ×4 subprotocol, the number of channels
increments by 4.
In a ×8 subprotocol, the number of channels
increment by 8.
Description
Stratix IV Device Handbook Volume 3
Reference
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1–7
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