EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1006

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–48
Table 1–14. MegaWizard Plug-In Manager Options (Protocol Settings —GIGE and XAUI) (Part 2 of 3)
Stratix IV Device Handbook Volume 3
Create an rx_disperr port to
indicate 8B/10B decoder has
detected a disparity error.
Create a tx_invpolarity port to
allow Transmitter polarity inversion.
Create an rx_runningdisp port to
indicate the current running
disparity of the 8B/10B decoded
byte.
Create an rx_rmfifofull port to
indicate when the rate match FIFO
is full.
Create an rx_rmfifoempty port to
indicate when the rate match FIFO
is empty.
Create an
rx_rmfifodatainserted port to
indicate when data is inserted in the
rate match FIFO.
Create an rx_rmfifodatadeleted
port to indicate when data is deleted
in the rate match FIFO.
ALTGX Setting
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric.This signal is
asserted high if the received 10-bit code or data
group has a disparity error. When this signal goes
high, rx_errdetect also is asserted high.
This optional port allows you to dynamically
reverse the polarity of every bit of the data word
fed to the serializer in the transmitter data path.
Use this option when the positive and negative
signals of the differential output from the
transmitter (tx_dataout) are erroneously
swapped on the board.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric. This signal
is asserted high when the current running
disparity of the 8B/10B decoded byte is negative.
This signal is low when the current running
disparity of the 8B/10B decoded byte is positive.
This option creates the output port
rx_rmfifofull. It is a status flag that the rate
match block forwards to the FPGA fabric. This
indicates when the rate match FIFO block is full
(20 words). This signal remains high as long as
the FIFO is full and is asynchronous to the
receiver data path.
This option creates the output port
rx_rmfifoempty. It is a status flag that the rate
match block forwards to the FPGA fabric. This
indicates when the rate match FIFO block is empty
(five words). This signal remains high as long as
the FIFO is empty and is asynchronous to the
receiver data path.
This option creates the output port
rx_rmfifodatainserted flag. It is a status flag
that the rate match block forwards to the FPGA
fabric. The rx_rmfifodatainserted flag is
asserted when a rate match pattern byte is
inserted to compensate for the PPM difference in
reference clock frequencies between the
upstream transmitter and the local receiver.
This option creates the output port
rx_rmfifodatadeleted. It is a status flag that
the rate match block forwards to the FPGA fabric.
The rx_rmfifodatadeleted flag is asserted
when a rate match pattern byte is deleted to
compensate for the PPM difference in reference
clock frequencies between the upstream
transmitter and the local receiver.
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
“8B/10B Decoder” section in the
Transceiver Architecture in
Stratix IV Devices
“Transmitter Polarity Inversion”
section in the
Architecture in Stratix IV Devices
chapter.
“Rate Match (Clock Rate
Compensation) FIFO” section in
the
Stratix IV Devices
“Rate Match (Clock Rate
Compensation) FIFO” section in
the
Stratix IV Devices
“Rate Match (Clock Rate
Compensation) FIFO” section in
the
Stratix IV Devices
“Rate Match (Clock Rate
Compensation) FIFO” section in
the
Stratix IV Devices
Transceiver Architecture in
Transceiver Architecture in
Transceiver Architecture in
Transceiver Architecture in
February 2011 Altera Corporation
Reference
Transceiver
—
chapter.
chapter.
chapter.
chapter.
chapter.
Protocol Settings