EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 943

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EP4SE530H40I3

Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H40I3

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Examples
February 2011 Altera Corporation
Different Dynamic Reconfiguration Modes Involved
1. Channel and CMU PLL reconfiguration mode:
2. Channel and CMU PLL select reconfiguration mode:
3. The rx_tx_duplex_sel[1:0] port allows you to reconfigure the transmitter and
4. PMA controls reconfiguration mode used to configure the PMA settings for all the
For more information, refer to
on page
.mif Generation
The following .mifs are required for this example:
For more information, refer to
Various Dynamic Reconfiguration Transactions
The following dynamic reconfiguration transactions are required
page
1
1
receiver channels to operate at the different data rates.
channels.
For the seven regular transceiver channels, you must generate two .mifs. Use one
to move from a data rate of 2.5 Gbps to 5 Gbps and the other to revert back to
2.5 Gbps.
For the for PMA-only channels, you must generate two .mifs. Use one to move
from a data rate of 3.125 Gbps to 5 Gbps and the other to revert back to 3.125 Gbps.
.mif write transaction—for more information, refer to
Reconfiguration Mode Details” on page 5–24
Transmitter PLL Select Mode Details” on page
Reconfiguring PMA controls—for more information, refer to
Reconfiguring PMA Controls” on page
5–94:
is used for reconfiguring the seven regular transceiver channels from one data
rate to another using the same CMU0 PLL (in GXBR2)
is used for reconfiguring the four PMA-only channels from one data rate to
another using the CMU0 PLL (in GXBR0) and CMU1 PLL (GXBR0)
5–19.
This mode is chosen because both the receiver and transmitter of the
regular channels must be re-configured using a single CMU.
This mode is chosen because both the receiver and transmitter of the
regular channels must be re-configured and more than one CMU can be
used.
“Transceiver Channel Reconfiguration Mode Details”
“Memory Initialization File (.mif)” on page
5–13.
and
Stratix IV Device Handbook Volume 2: Transceivers
5–47.
“Channel Reconfiguration with
“Channel and CMU PLL
“Dynamically
“Example 1” on
5–20.
5–97

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