EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 193

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
Table 6–4. Default Slew Rate Settings
February 2011 Altera Corporation
1.2-V, 1.5-V, 1.8-V, 2.5-V LVCMOS, and 3.3-V LVTTL/LVCMOS
SSTL-2, SSTL-18, SSTL-15, HSTL-18, HSTL-15, and HSTL-12
3.0-V PCI/PCI-X
LVDS_E_1R, mini-LVDS_E_1R, and RSDS_E_1R
LVDS_E_3R, mini-LVDS_E_3R, and RSDS_E_3R
Programmable Slew Rate Control
1
1
1
Table 6–3. Programmable Current Strength (Part 2 of 2)
Altera recommends performing IBIS or SPICE simulations to determine the best
current strength setting for your specific application.
The output buffer for each Stratix IV device regular- and dual-function I/O pin has a
programmable output slew-rate control that you can configure for low-noise or
high-speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. A slower slew rate can help reduce system noise, but adds
a nominal delay to the rising and falling edges. Each I/O pin has an individual
slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis.
You cannot use the programmable slew rate feature when using OCT R
The Quartus II software allows four settings for programmable slew rate control—0,
1, 2, and 3—where 0 is slow slew rate and 3 is fast slew rate.
default slew rate settings from the Quartus II software.
You can use faster slew rates to improve the available timing margin in
memory-interface applications or when the output pin has high-capacitive loading.
Altera recommends performing IBIS or SPICE simulations to determine the best slew
rate setting for your specific application.
HSTL-12 Class I
HSTL-12 Class II
Notes to
(1) The default setting in the Quartus II software is 50-
(2) The 3.3-V LVTTL and 3.3-V LVCMOS are supported using V
HSTL and SSTL Class I I/O standards. The default setting is 25-
Class II I/O standards.
I/O Standard
Table
I/O Standard
6–3:
I
OH
/ I
Setting (mA) for
Column I/O Pins
Ω
OL
12, 10, 8, 6, 4
OCT R
Current Strength
16
S
CCIO
Slew Rate Option
without calibration for all non-voltage reference and
Ω
and V
(Note
OCT R
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
CCPD
1),
S
without calibration for HSTL and SSTL
at 3.0 V.
Stratix IV Device Handbook Volume 1
(2)
Figure 6–4
I
OH
/ I
Setting (mA) for
OL
Row I/O Pins
Default Slew Rate
Current Strength
8, 6, 4
S
lists the
—
.
3
3
3
3
3
6–21