EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 981

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EP4SE530H40I3

Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H40I3

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Table 1–5. MegaWizard Plug-In Manager Options (RX Analog Screen) (Part 2 of 2)
February 2011 Altera Corporation
What is the receiver common
mode voltage (RX V
Force signal detection.
What is the signal detect
threshold?
Use external receiver
termination.
What is the receiver
termination resistance?
ALTGX Setting
CM
)?
The receiver common mode voltage is
programmable to 0.82 V or 1.1 V.
In PCIe mode, this option disables the
signal threshold detect circuit for the
receiver CDR. The receiver CDR no
longer depends on the signal detect
criterion to switch from LTR to LTD
mode.
Use this option in PCIe or Basic mode
with the 8B/10B block enabled and the
rx_signaldetect port selected to
determine the threshold level for the
signal detect circuit.
Select this option if you want to use an
external termination resistor instead of
differential on-chip termination (OCT). If
checked, this option turns off the
receiver OCT.
This option allows you to select the
receiver differential termination value.
The settings allowed are:
PIPE mode—The levels are fixed.
Basic mode—A range of values
depending on the data rate are
available. The levels will be
determined after characterization.
85 Ω
100 Ω
120 Ω
150 Ω.
Description
“Receiver Channel Datapath” section in the
Transceiver Architecture in Stratix IV Devices
chapter.
“Signal Threshold Detection Circuitry” section
in the
Devices
“Signal Threshold Detection Circuitry” section
in the
Devices
“Programmable Differential On-Chip
Termination” section in the
Architecture in Stratix IV Devices
“Programmable Differential On-Chip
Termination” section in the
Architecture in Stratix IV Devices
the
Stratix IV Devices
DC and Switching Characteristics for
Transceiver Architecture in Stratix IV
Transceiver Architecture in Stratix IV
chapter.
chapter.
Stratix IV Device Handbook Volume 3
section.
Reference
Transceiver
Transceiver
chapter.
chapter, and
1–23

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