EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1047

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Example 1: Fibre Channel Protocol Application
Figure 2–12. FC4G Instance Settings (Word Aligner Screen)
February 2011 Altera Corporation
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Word Aligner screen—The fibre channel protocol requires that you use K28.5 to
align the byte boundary. In the What is the word alignment pattern? option, set
one of the 10-bit disparity values to K28.5. The word aligner automatically detects
when the other disparity value is received.
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Select the rx_patterndetect and rx_syncstatus signals. The
rx_patterndetect signal indicates whenever the word alignment pattern is
detected in the word boundary.
Click Finish to exit the ALTGX MegaWizard Plug-In Manager.
Stratix IV Device Handbook Volume 3
2–29