EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1019

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

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SIV53002-4.1
Stratix IV Device Handbook Volume 3
February 2011
February 2011
SIV53002-4.1
This chapter describes the Altera-recommended basic design flow that simplifies
Stratix
Use the following design flow techniques to simplify transceiver implementation. The
“Guidelines to Debug Transceiver-Based Designs” on page 2–14
to trouble-shoot transceiver-based designs. An example of a fibre channel protocol
application is also described in this chapter.
The transceiver-based design is divided into phases and are detailed in the following
sections:
■
■
■
■
■
■
Figure 2–1
design flow stages include architecture, functional simulation, compilation, and
verification. Each stage of the design flow is explained in the sections that follow.
“Architecture” on page 2–3
“Implementation and Integration” on page 2–6
“Compilation” on page 2–10
“Verification” on page 2–12
“Functional Simulation” on page 2–12
“Example 1: Fibre Channel Protocol Application” on page 2–17
®
IV GX transceiver-based designs.
shows the design flow chart of the different stages of the design flow. The
2. Transceiver Design Flow Guide for
Stratix IV Devices
provides guidelines
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