EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 666

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–222
Table 1–77. Stratix IV GX and GT ALTGX Megafunction Ports: PCIe Interface (Part 3 of 4)
Stratix IV Device Handbook Volume 2: Transceivers
tx_detectrxloopback
pipestatus
pipephydonestatus
Port Name
Output
Output
Output
Input/
Input
Clock Domain
Asynchronous
signal
N/A
N/A
Receiver detect or PCIe loopback control.
■
■
■
PCIe receiver status port.
■
■
■
PHY function completion indicator.
■
■
■
Functionally equivalent to the
txdetectrx/loopback signal defined in the
PCIe specification revision 2.0.
When asserted high in the P1 power state with
the tx_forceelecidle signal asserted—the
transmitter buffer begins the receiver detection
operation. After the receiver detect completion
is indicated on the pipephydonestatus port,
this signal must be de-asserted.
When asserted high in the P0 power state with
the tx_forceelecidle signal de-asserted—
the transceiver datapath gets dynamically
configured to support parallel loopback, as
described in
on page
Functionally equivalent to the rxstatus[2:0]
signal defined in the PCIe specification revision
2.0.
Synchronized with tx_clock.
The width of this signal is 3 bits per channel.
The encoding of receiver status on the
pipestatus port is as follows:
■
■
■
■
■
■
■
■
Functionally equivalent to the phystatus signal
defined in the PCIe specification revision 2.0.
Assert this signal high for one parallel clock
cycle to communicate completion of several
PHY functions, such as power state transition,
receiver detection, and signaling rate change
between Gen1 (2.5 Gbps) and Gen2 (5 Gbps).
Synchronized with tx_clkout.
000—Received data OK
001—1 skip added
010—1 skip removed
011—Receiver detected
100—8B/10B decoder error
101—Elastic buffer overflow
110—Elastic buffer underflow
111—Received disparity error
Chapter 1: Transceiver Architecture in Stratix IV Devices
1–194.
“PCIe Reverse Parallel Loopback”
Description
February 2011 Altera Corporation
Transceiver Port Lists
Channel
Channel
Channel
Scope