EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 464

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–20
Table 1–7. TX Phase Compensation FIFO Modes
Stratix IV Device Handbook Volume 2: Transceivers
Low-Latency
High-Latency
Non-Bonded Functional
Bonded Functional
Modes
f
Table 1–7
For more information about the TX phase compensation FIFO, refer to the
“Limitations of the Quartus II Software-Selected Transmitter Phase Compensation
FIFO Write Clock” section of the
In PCIe functional mode, the input data comes from the PCIe interface. In all other
functional modes, the input data comes directly from the FPGA fabric.
The output from the TX phase compensation FIFO is used by the byte serializer block,
8B/10B encoder, or serializer block.
phase compensation FIFO outputs are provided to these blocks.
Table 1–8. Output Data Destination Block for the TX Phase Compensation FIFO Output Data
If you select:
single-width mode and channel
width = 16 or 20
If you select:
double-width mode and
channel width = 32 or 40
Input Data
Output Data Destination Block
Byte Serializer
lists the TX phase compensation FIFO modes.
The FIFO is four words deep. Latency through the FIFO is two to three FPGA fabric
parallel clock cycles (pending characterization).
The default setting for every mode.
The FIFO is eight words deep. The latency through the FIFO is four to five FPGA parallel
cycles (pending characterization).
For example, in GIGE mode, the read port of the phase compensation FIFO is clocked
by the low-speed parallel clock. The write clock is fed by the tx_clkout port of the
associated channel.
For example, in XAUI mode, the write clock of the FIFO is clocked by coreclkout
provided by the CMU0 clock divider block. You can clock the write side using
tx_coreclk provided from the FPGA fabric by enabling the tx_coreclk port in the
ALTGX MegaWizard Plug-In Manager. If you use this port, ensure that there is
0 parts-per-million (PPM) difference in frequency between the write and read side. The
Quartus
Editor.
®
II software requires that you provide a 0 PPM assignment in the Assignment
If you select:
single-width mode and
channel width = 8 and
8B/10B encoder enabled
If you select:
double-width mode and
channel width = 16 and
8B/10B encoder enabled
Transceiver Clocking in Stratix IV Devices
8B/10B Encoder
Table 1–8
Chapter 1: Transceiver Architecture in Stratix IV Devices
Description
lists the conditions under which the TX
If you select:
low-latency PCS bypass mode
enabled or single-width mode and
channel width = 8 or 10
If you select:
low-latency PCS bypass mode
enabled or double-width mode
and channel width = 16 or 20
February 2011 Altera Corporation
Transceiver Block Architecture
Serializer
chapter.