EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 509

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–52. Word Aligner with 10-Bit PMA-PCS Manual Alignment Mode
February 2011 Altera Corporation
rx_enapatternalign
rx_dataout[10..0]
rx_patterndetect
rx_syncstatus
1
rx_clkout
Two status signals, rx_syncstatus and rx_patterndetect, with the same latency as
the datapath, are forwarded to the FPGA fabric to indicate the word aligner status.
After receiving the first word alignment pattern after the rx_enapatternalign signal
is asserted high, both the rx_syncstatus and rx_patterndetect signals are driven
high for one parallel clock cycle. Any word alignment pattern received thereafter in
the same word boundary causes only the rx_patterndetect signal to go high for one
clock cycle. Any word alignment pattern received thereafter in a different word
boundary causes the word aligner to re-align to the new word boundary only if the
rx_enapatternalign signal is held high. The word aligner asserts the rx_syncstatus
signal for one parallel clock cycle whenever it re-aligns to the new word boundary.
Figure 1–52
PMA-PCS interface mode. In this example, a /K28.5/ (10'b0101111100) is specified as
the word alignment pattern. The word aligner aligns to the /K28.5/ alignment
pattern in cycle n because the rx_enapatternalign signal is asserted high. The
rx_syncstatus signal goes high for one clock cycle, indicating alignment to a new
word boundary. The rx_patterndetect signal also goes high for one clock cycle to
indicate initial word alignment. At time n + 1, the rx_enapatternalign signal is
de-asserted to instruct the word aligner to lock the current word boundary. The
alignment pattern is detected again in a new word boundary across cycles n + 2 and
n + 3. The word aligner does not align to this new word boundary because the
rx_enapatternalign signal is held low. The /K28.5/ word alignment pattern is
detected again in the current word boundary during cycle n + 5, causing the
rx_patterndetect signal to go high for one parallel clock cycle.
If the word alignment pattern is known to be unique and does not appear between
word boundaries, you can constantly hold the rx_enapatternalign signal high
because there is no possibility of false word alignment. If there is a possibility of the
word alignment pattern occurring across word boundaries, you must control the
rx_enapatternalign signal to lock the word boundary after the desired word
alignment is achieved to avoid re-alignment to an incorrect word boundary.
111110000
shows the manual alignment mode word aligner operation with 10-bit
n
0101111100
n + 1
111110000
n + 2
1111001010
n + 3
1000000101
Stratix IV Device Handbook Volume 2: Transceivers
n + 4
111110000
n + 5
0101111100
1–65