EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 115
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 4: DSP Blocks in Stratix IV Devices
Software Support
Table 4–9. DSP Block Dynamic Signals (Part 2 of 2)
Software Support
February 2011 Altera Corporation
accum_sload
zero_chainout
zero_loopback
rotate
shift_right
Total Signals per Half Block
clock0
clock1
clock2
clock3
ena0
ena1
ena2
ena3
aclr0
aclr1
aclr2
aclr3
Total Count per Full Block
Signal Name
f
Altera provides two distinct methods for implementing various modes of the DSP
block in a design—instantiation and inference. Both methods use the following
Quartus II megafunctions:
■
■
■
■
To use the DSP block, instantiate the megafunctions in the Quartus II software.
Alternatively, with inference, create an HDL design and synthesize it using a
third-party synthesis tool (such as LeonardoSpectrum™, Synplify, or Quartus II
Native Synthesis) that infers the appropriate megafunction by recognizing
multipliers, multiplier adders, multiplier accumulators, and shift functions. Using
either method, the Quartus II software maps the functionality to the DSP blocks
during compilation.
For instructions about using these megafunctions and the MegaWizard Plug-In
Manager, refer to Quartus II software Help.
lpm_mult
altmult_add
altmult_accum
altfp_mult
Dynamically specifies whether the accumulator value is zero.
■
■
Dynamically specifies whether the chainout value is zero.
Dynamically specifies whether the loopback value is zero.
rotate = 1, the rotation feature is enabled
shift_right = 1, the shift right feature is enabled
DSP-block-wide clock signals.
Input and Pipeline Register enable signals.
DSP block-wide asynchronous clear signals (active low).
accum_sload = 0, accumulation input is from the output registers
accum_sload = 1, accumulation input is set to zero
Function
Stratix IV Device Handbook Volume 1
Count
11
34
1
1
1
1
1
4
4
4
4–35
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