EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 465

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
f
1
An optional tx_phase_comp_fifo_error port is available in all functional modes to
indicate a receiver phase compensation FIFO overflow or under-run condition. The
tx_phase_comp_fifo_error signal is asserted high when the TX phase compensation
FIFO either overflows or under-runs due to any frequency PPM difference between
the FIFO read and write clocks. If the tx_phase_comp_fifo_error flag is asserted,
verify the FPGA fabric-transceiver interface clocking to ensure that there is 0 PPM
difference between the TX phase compensation FIFO read and write clocks.
Byte Serializer
The byte serializer divides the input datapath by two. This allows you to run the
transceiver channel at higher data rates while keeping the FPGA fabric interface
frequency within the maximum limit stated in the “Interface Frequency” section in
the
two-byte-wide datapath to a one-byte-wide datapath. In double-width mode, it
converts the four-byte-wide datapath to a two-byte-wide datapath. It is optional in
configurations that do not exceed the FPGA fabric-transceiver interface maximum
frequency limit.
For example, if you want to run the transceiver channel at 6.25 Gbps, without the byte
serializer in double-width mode, the FPGA fabric interface clock frequency must be
312.5 MHz (6.25/20). This violates the FPGA fabric interface frequency limit. When
you use the byte serializer, the FPGA fabric interface frequency is 156.25 MHz
(6.25G/40). You can enable the byte serializer in single-width or double-width mode.
The byte deserializer is required in configurations that exceed the FPGA
fabric-transceiver interface maximum frequency limit.
For more information about the maximum frequency limit for the transceiver
interface, refer to the
Figure 1–15
width, refer to
Figure 1–15. Byte Serializer Datapath in Single-Width Mode
Notes to
(1) For the datain[] and dataout[] port widths, refer to
(2) The datain signal is the input from the FPGA fabric that has already passed through the TX phase compensation
FIFO.
DC and Switching Characteristics
TX Phase Compensation FIFO Status Signal
Single-Width Mode
Figure
shows the byte serializer datapath in single-width mode. For data port
1–15:
Table
1–9.
Device Datasheet for Stratix IV Devices section.
datain[]
chapter. In single-width mode, it converts the
Byte Serializer
/2
Table
Stratix IV Device Handbook Volume 2: Transceivers
dataout[]
1–9.
Low-Speed Parallel
(Note
Clock
1),
(2)
1–21