EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 911

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–34. Read Transaction in Data Rate Division in Transmitter Mode
Note to
(1) For this example, the existing local divider settings of the transmitter channel are Divide by 2. Therefore, the value read out at
February 2011 Altera Corporation
rate_switch_out[1:0] is 2'b01.
logical_channel_address (1)
Figure
reconfig_mode_sel[2:0]
rate_switch_out[1:0]
5–34:
f
1
reconfig_clk
data_valid
For this example, the value set in the What is the number of channels controlled by
the reconfig controller? option of the ALTGX_RECONFIG MegaWizard Plug-In
Manager is 4. Therefore, the logical_channel_address input is 2 bits wide. Also, you
must read the existing local divider settings of the transmitter channel whose logical
channel address is 2'b01.
division in transmitter mode.
busy
Do not perform a read transaction in date rate division in transmitter mode if
rate_switch_out[1:0] is not selected in the ALTGX_RECONFIG MegaWizard
Plug-In Manager.
For more information about reset, refer to the “Reset Sequence when Using Dynamic
Reconfiguration with the Channel and TX PLL select/reconfig Option” section in the
Reset Control and Power Down in Stratix IV Devices
read
2'bXX
3'bXXX
2'bXX
Figure 5–34
Invalid output
shows a read transaction waveform in data rate
3'b011
2'b01
Stratix IV Device Handbook Volume 2: Transceivers
chapter.
2'bXX
2'b01
5–65