EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 815
EP4SE530H40I3
Manufacturer Part Number
EP4SE530H40I3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40I3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transceiver Reset Sequences
February 2011 Altera Corporation
As shown in
follow these reset steps:
1. After power up, assert pll_powerdown for a minimum period of t
2. Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset signals
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high,
4. For the receiver operation, after de-assertion of busy signal, wait for a minimum of
5. Wait for the rx_freqlocked signal from each channel to go high. The
6. In a bonded channel group, when the rx_freqlocked signals of all the channels
time between markers 1 and 2).
asserted during this time period. After you de-assert the pll_powerdown signal, the
transmitter PLL starts locking to the transmitter input reference clock.
de-assert the tx_digitalreset signal. At this point, the transmitter is ready for
data traffic.
two parallel clock cycles to de-assert the rx_analogreset signal. After
rx_analogreset is de-asserted, the receiver CDR of each channel starts locking to
the receiver input reference clock.
rx_freqlocked signal of each channel may go high at different times (indicated by
the slashed pattern at marker 7).
has gone high, from that point onwards, wait for at least t
parallel clock to be stable, then de-assert the rx_digitalreset signal (marker 8).
At this point, all the receivers are ready for data traffic. Note that rx_digitalreset
must not be released if there is no data present at the receiver pins to avoid
overflow/underflow of the phase compensation FIFOs.
Figure
4–4, for the receiver CDR in automatic lock mode configuration,
Stratix IV Device Handbook Volume 2: Transceivers
LTD_Auto
pll_powerdown
for the receiver
(the
4–9
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