EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1054

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

2–36
Document Revision History
Table 2–7. Document Revision History (Part 1 of 2)
Stratix IV Device Handbook Volume 3
February 2011
November 2009
June 2009
March 2009
Date
Phase 3—Compilation
Phase 4—Simulating the Design
Version
Create Data Processing and Other User Logic
For this example, you must implement the 8B/10B encoder and decoder in the FPGA
fabric.
and the system logic controls for all channels in the FPGA fabric. This block diagram
is a representation of a typical system and may not exactly show the different blocks
in a practical application. Interface all the logic blocks with the transceiver.
If you would like to add SignalTap for verification, first complete synthesis, then add
the transceiver-FPGA fabric or other user logic signals in SignalTap. Lastly, compile
the design to generate the .sof.
Assign pins for the input and output signals in your design. The Quartus II software
versions 8.1 and earlier do not allow pin assignments for the Stratix IV GX device.
Set the OCT values for the transceiver serial pins, add timing constraints for the clocks
and data paths in your logic, then compile the design.
To simulate the design, follow the steps outlined in
page
Table 2–7
4.0
4.1
3.1
3.0
2–12.
Figure 2–17 on page 2–35
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Applied new template.
Updated chapter title.
Minor text edits
Added Table 2–3, Table 2–4, Table 2–5, and Table 2–6.
Minor text edits.
Updated the “Introduction”, “Power Supplies”, “Transceiver Configuration”, “Clocking”,
“Create Transceiver Instances”, “Create Dynamic Reconfiguration Controller Instances”,
“Create Data Processing and Other User Logic”, “Functional Simulation” sections.
Added the “Board Design Requirements”, “Gear Boxing Logic”, “Guidelines to Debug the
FPGA Logic and the Transceiver Interface”, and “Guidelines to Debug System
Issues” sections.
Added introductory sentences to improve search ability.
Add “Power Supplies” on page 2–6
Updated “Dynamic Reconfiguration” on page 2–4
Text edits
lists the revision history for this chapter.
shows the logic on the transmitter and receiver side
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Changes
“Functional Simulation” on
February 2011 Altera Corporation
Document Revision History
Level