EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 528

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–84
Figure 1–68. Rate Match Deletion in Basic Single-Width Mode
Stratix IV Device Handbook Volume 2: Transceivers
rx_rmfifodatadeleted
dataout
datain
1
In Basic single-width mode, the rate match FIFO is capable of compensating for up to
±300 PPM (600 PPM total) difference between the upstream transmitter and the local
receiver reference clock.
To enable the rate match FIFO in Basic single-width mode, the transceiver channel
must have both the transmitter and receiver channel instantiated. You must select the
Receiver and Transmitter option in the What is the operation mode? field in the
ALTGX MegaWizard Plug-In Manager. You must also enable the 8B/10B
encoder/decoder in Basic single-width mode with rate match FIFO enabled.
Depending on your proprietary protocol implementation, you can select two 20-bit
rate match patterns in the ALTGX MegaWizard Plug-In Manager under the What is
the rate match pattern1 and What is the rate match pattern2 fields. Each of the two
programmed 20-bit rate match patterns consists of a 10-bit skip pattern and a 10-bit
control pattern. You must choose 10-bit code groups that have a neutral disparity as
the skip patterns. The rate match FIFO operation begins after the word aligner
synchronization status rx_syncstatus goes high. When the rate matcher receives
either of the two 10-bit control patterns followed by the respective 10-bit skip pattern,
it inserts or deletes the 10-bit skip pattern as necessary to avoid the rate match FIFO
from overflowing or under running.
The rate match FIFO can delete a maximum of four skip patterns from a cluster, if
there is one skip pattern left in the cluster after deletion. The rate match FIFO can
insert a maximum of four skip patterns in a cluster, if there are no more than five skip
patterns in the cluster after insertion. Two flags, rx_rmfifodatadeleted and
rx_rmfifodatainserted, indicating rate match FIFO deletion and insertion events,
respectively, are forwarded to the FPGA fabric.
Figure 1–68
skip patterns are required to be deleted. In this example, /K28.5/ is the control
pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a
/K28.5/ control pattern followed by two /K28.0/ skip patterns. The second skip
cluster has a /K28.5/ control pattern followed by four /K28.0/ skip patterns. The rate
match FIFO deletes only one /K28.0/ skip pattern from the first skip cluster to
maintain at least one skip pattern in the cluster after deletion. Two /K28.0/ skip
patterns are deleted from the second cluster for a total of three skip patterns deletion
requirement.
Rate Match FIFO in Basic Single-Width Mode
K28.5
K28.5
First Skip Cluster
shows an example of rate match FIFO deletion in the case where three
K28.0
K28.0
K28.0
K28.5
K28.0
K28.5
Three Skip Patterns Deleted
Chapter 1: Transceiver Architecture in Stratix IV Devices
K28.0
K28.0
Second Skip Cluster
K28.0
K28.0
February 2011 Altera Corporation
K28.0
Transceiver Block Architecture
K28.0